For reducing current consumption in a dynamic random access memory (DRAM) during the standby time when only data retention is made, it is indispensable to reduce the current during the refresh operation (the operation of amplifying data read out to a bit line from memory cells connected to the word line associated with the refresh address, and of re-storing the read-out data via the bit line).
In the DRAM, where the storage capacity is becoming larger and larger and the miniaturization is advancing, attempts are being made to improve the worst case value of the data retention time of the memory cell by the fabrication process. By way of circuit designing countermeasures, such a technique consisting in providing 100 or more remedy sets, employing redundant cells, per one bank (e.g. 64 megabits) in order to eke out shortage of the retention time for certain memory cells, or such a technique consisting in remedying with anti-fuses in order to provide for substitution to redundant cells even after package assembling of the REAM device, has been developed. However, in case the retention time is increased through 200 ms or 300 ms to approaches to a limit, retention failure, termed retention time variation failure, tends to be produced due to unforeseen noises, including software errors. Hence, it is necessary to cope with such failure by a technique other than the above techniques.
Also, from the perspective of costs of the DRAM device, it is necessary to suppress the chip size penalty (that is, circuit increment for providing the retention time).
For a user, it is also necessary not to change the specifications of the DRAM device (interface) from those of a conventional product, that is, to maintain interchangeability with the conventional product, at the time of entry to or exiting from the standby time mode (self refresh). For application to a customer frequently repeating the entry to and exiting from the standby mode (self-refresh), such as a mobile phone terminal, it is necessary to reduce the operating current at the time of entry to or exiting from the standby time mode (self refresh).
As refresh control for the dynamic RAM (DRAM), there is disclosed in the Patent Publication 1, indicated hereinbelow, a configuration in which power consumption may be appreciably reduced by carrying out refreshing with two or more refresh periods associated with information retention time for the memory cells, in terms of plural word lines, to which is allocated a common refresh address, as a unit. In this technique, only certain memory cells where the retention time is in shortage are refreshed with a short period, e.g. of the order of 100 ms, while the remaining memory cells are refreshed with a longer period, e.g. of the order of 1 s, thereby reducing the standby current of the DRAM. The refresh period is sorted during wafer inspection every main word line (MWL) and the result of the sorting, that is, the short period or the long period, is recorded in a PROM enclosed in the DRAM. It is noted that a PROM array forms an adaptive refresh controller. When entry is made to self refresh, the totality of the main word lines are refreshed with the long period and, after time T, the refresh operation with the long term is repeated. Exiting from the self refresh is with ‘self refresh exit’.
The flowchart of FIG. 22, prepared by the present inventor, illustrates the adaptive refresh control described in the Patent Publication 1. On entry to the self refresh (step S601), the totality of main word lines is refreshed with the long period T (step S602). The main word line, registered in the PROM with the short refresh period (T/N), then is refreshed with a short period (T/N) (step S603). Except in case of exiting from self refresh (NO branching in a step S604), refresh with a short period (T/N) is repeated N times (steps S604, S605). After time T, refresh with the long period is repeated (steps S605 and S606). In case of exiting from self refresh in the steps S604, S606, processing transfers to the self refresh exit processing of a step S607.
There is also disclosed in e.g. the Patent Publication 2, indicated hereinbelow, a technique in which, at the time of entry to an operating mode carrying out only the data retention operation, the totality of bits are encoded (check bits are generated and stored), using an ECC (error correcting circuit), the refresh operation is carried out as the refresh period is elongated within the allowance range of error generation by the error correcting operation employing the check bit and, in returning (exiting) from the data retention mode to the normal operation, the error correcting operation is carried out using the data and the check bits by the ECC circuit, to carry out refresh with a period not shorter than the retention time of the memory cell. With the Patent Publication 2, the entire area in the chip is refreshed with the long period, such as about 1 s, to reduce the standby current of the DRAM. FIG. 23, prepared by the present inventors, illustrates the refresh control during standby time of the Patent Publication 2.
In entry to the low power consumption (SSR) mode, the totality of bits is encoded (steps S701, S702) and the correction operation is carried out by decoding the totality of bits at the time of exiting (steps S705, S706).
[Patent Publication 1]
JP Patent Publication Kokai JP-A-08-306184 (pages 4, 5 and FIG. 1)
JP Patent Publication Kokai JP-A-2002-56671 (page 3 and FIG. 1)